DDC232 Datasheet, PDF (17/28 Pages) Burr-Brown (TI) – 32-Channel, Current-Input Analog-to-Digital Converter

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In Figure 11, the first state is ncont state 8. The
DDC232 always powers up in the ncont mode. In this
case, the first state is 8 because CONV is initially
low. After the first two states, cont mode operation is
reached and the states begin toggling between 4 and
5. From now on, the input is being continuously
integrated, either on side A or side B. The time
needed for the m/r/az cycle, t_MRAZ, is the same time
DDC232
SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006
that determines the boundary between the cont and
ncont modes described earlier in the Overview
section. DVALID goes low after CONV toggles in
time t_CMDR, indicating that data is ready to be
retrieved.
See Figure 12 for the timing diagram of the internal
operations occurring during continuous mode
operation. Table 6 gives the timing specifications of
the internal operations occurring during continuous
mode operation.
End Integration Side A
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
CONV
t_INT
t_INT
A/D Conversion
Odd Channels (Internal)
A/D Conversion
Even Channels (Internal)
DVALID
Side A
t_ADCONV
t_ADRST
Side A
t_ADCONV
Side B
t_ADRST
t_IRST
Side B
t_IRST
Side A
Side A
Data Ready
Side B
Data Ready
Figure 12. Timing Diagram for DDC232 Internal Operation in Continuous Mode
Table 6. Timing for the Internal Operation in Continuous Mode
SYMBOL DESCRIPTION
t_INT
t_ADCONV
t_ADRST
t_IRST
Integration Period (continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
Integrator Reset Time (internally controlled)
Low-Power Mode
(CLK = 5MHz)
MIN
TYP
MAX
320
1,000,000
135.6
3.2
36
High-Speed Mode
(CLK = 9.6MHz)
MIN
TYP
MAX
162
1,000,000
TBD
TBD
TBD
UNITS
µs
µs
µs
µs
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