DDC232 Datasheet, PDF (14/28 Pages) Burr-Brown (TI) – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006
DIGITAL INTERFACE
The digital interface of the DDC232 outputs the
digital results via a synchronous serial interface
consisting of a data clock (DCLK), a valid data pin
(DVALID), a serial data output pin (DOUT), and a
serial data input pin (DIN). The integration and
conversion process is fundamentally independent of
the data retrieval process. Consequently, the CLK
and DCLK frequencies need not be the same,
though for best performance, it is highly
recommended that they be derived from the same
clocking source to keep their phase relationship
constant. DIN is only used when multiple converters
are cascaded and should be tied to DGND
otherwise. Depending on t_INT, CLK, and DCLK, it is
possible to daisy-chain multiple converters. This
greatly simplifies the interconnection and routing of
the digital outputs in those applications where a large
number of converters are needed. Configuration of
the DDC232 is set by a dedicated register addressed
using the DIN_CFG and CLK_CFG pins.
System and Data Clocks (CLK and CONV)
The system clock is supplied to CLK and the data
clock is supplied to DCLK. Make sure the clock
signals are clean—avoid overshoot or ringing. For
best performance, generate both clocks from the
same clock source. DCLK should be disabled by
taking it low after the data has been shifted out or
while CONV is transitioning.
When using multiple DDC232s, pay close attention
to the DCLK distribution on the printed circuit board
(PCB). In particular, make sure to minimize skew in
the DCLK signal because this can lead to timing
violations in the serial interface specifications. See
the Cascading Multiple Converters section for more
details.
Data Valid (DVALID)
The DVALID signal indicates that data is ready. Data
retrieval may begin after DVALID goes low. This
signal is generated using an internal clock divided
down from the system clock, CLK. The phase
relationship between this internal clock and CLK is
set when power is first applied and is random. Since
the user must synchronize CONV with CLK, the
DVALID signal will have a random phase relationship
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with CONV. This uncertainty is ± 1/f_CLK. Polling
DVALID eliminates any concern about this
relationship. If data read back is timed from CONV,
wait the maximum value of t₇ or t₈ to insure data is
valid.
Reset (RESET)
The DDC232 is reset asynchronously by taking the
RESET input low, as shown in Figure 9. Make sure
the release pulse is at least 1µs wide. After resetting
the DDC232, wait at least four conversions before
using the data. It is very important that RESET is
glitch-free to avoid unintentional resets.
RESET
> 1µs
Figure 9. Reset Timing
Conversion Rate
The conversion rate of the DDC232 is set by a
combination of the integration time (determined by
the user) and the speed of the A/D conversion
process. The A/D conversion time is primarily a
function of the system clock (CLK) speed. One A/D
conversion cycle encompasses the conversion of two
signals (one side of each dual integrator feeding the
modulator) and the reset time for each of the
integrators involved in the two conversions. In most
situations, the A/D conversion time is shorter than
the integration time. If this condition exists, the
DDC232 will operate in the continuous mode. When
the DDC232 is in the continuous mode, the sensor
output is continuously integrated by one of the two
sides of each input.
In the event that the A/D conversion takes longer
than the integration time, the DDC232 will switch into
a non-continuous mode. In non-continuous mode,
the A/D converter is not able to keep pace with the
speed of the integration process. Consequently, the
integration process is periodically halted until the
digitizing process catches up. These two basic
modes of operation for the DDC232—continuous and
non-continuous modes—are described below.
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