DDC232 Datasheet, PDF (13/28 Pages) Burr-Brown (TI) – 32-Channel, Current-Input Analog-to-Digital Converter

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Bit 11 Bit 10 Bit 9
Range[2] Range[1] Range[0]
Bit 8
Format
DDC232
SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006
Configuration Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pwr/Spd Clk_4x
0
0
0
0
0
Test
Bits 11–9
Bit 8
Bit 7
Range[2:0] Analog Input Range
000: 12.5pC
001: 50pC
010: 100pC
011: 150pC
100: 200pC
101: 250pC
110: 300pC
111: 350pC (default)
Format
0 = 16-Bit Output
1 = 20-Bit Output (default)
Format selects how many bits are used in the data output word.
Pwr/Spd
0 = Low-Power Mode (default)
1 = High-Speed Mode (DDC232CK Only)
Pwr/Spd BIT
0
1 ⁽²⁾
MODE
Low-Power
High-Speed ⁽²⁾
TYPICAL
POWER/CHANNEL (mW)
7
10
(1) Assumes Clk_4x = 0.
(2) Only the DDC232CK supports High-Speed mode.
MAXIMUM CLK
FREQUENCY (MHz)⁽¹⁾
5
10
MAXIMUM
DATA RATE (kHz)
3.125
6
Bit 6
Clk_4x (System Clock Divider)
0 = Internal Clock Divider = 1 (default)
1 = Internal Clock Divider = 4
The Clk_4x input enables an internal divider on the system clock. When Clk_4x = 1, the system
clock is divided by 4. This allows a 4X faster system clock, which in turn provides a finer
quantization of the integration time because the CONV signal needs to be synchronized with the
system clock for the best performance.
Clk_4x BIT
0
1
CLK DIVIDER VALUE
1
4
CLK FREQUENCY
5MHz
20MHz
INTERNAL CLOCK FREQUENCY
5MHz
5MHz
Bits 5–1
Bit 0
00000
Test Mode
0 = Test Mode Off (default)
1 = Test Mode On
When Test Mode is used, the inputs (IN1 through IN32) are disconnected from the DDC232
integrators to enable the user to measure a zero input signal regardless of the current supplied
to the inputs. The test mode works with both the continuous and non-continuous modes.
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