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CS4226 Datasheet, PDF (7/60 Pages) Cirrus Logic – Surround Sound Codec
CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C; VD+, VA+ = 5V ±5%;
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30 pF)
Parameter
I2C® Mode (SPI/I2C = 1)
Symbol
Min
(Note 12)
Max
Units
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 13)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
fscl
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
tr
tf
tsusp
-
100
kHz
4.7
µs
4.0
µs
4.7
µs
4.0
µs
4.7
µs
0
µs
250
ns
1
µs
300
ns
4.7
µs
Notes: 12. I2C is a registered trademark of Philips Semiconductors.
13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop Start
Repeated
Start
Stop
SDA
SCL
t buf
t hdst
t high
t hdst
tf
t low t hdd
t sud
t sust
tr
t susp
S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only; VD+, VA+ = 5V ±5%)
Parameter
Input Resistance
Input Voltage
Input Hysteresis
Input Sample Frequency
CLKOUT Jitter
CLKOUT Duty Cycle (high time/cycle time)
Symbol Min Typ Max Units
(Note 14)
ZN
VTH
VHYST
FS
-
10
200
-
-
50
30
-
-
200
-
kΩ
-
mVpp
-
mV
50
kHz
-
ps RMS
(Note 15)
40
50
60
%
Notes: 14. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384×Fs and 512×Fs as selected output frequency.
15. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.
DS188F1
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