CS4226 Datasheet, PDF (40/60 Pages) Cirrus Logic – Surround Sound Codec

CDB4226
2) the LRCK or LRCKAUX inputs to the CS4226,
3) a 1 Fs, 256 Fs, 384 Fs, or 512 Fs crystal con-
nected between XTI and XTO on the CS4226,
or
4) a 1 Fs, 256 Fs, 384 Fs, or 512 Fs clock connect-
ed to XTI on the CS4226 from the XT clock
line on the DSP port, DSP_HDR.
The clock source is chosen by setting the Clock
Source bits, CS2/1/0 in the Clock Mode Byte, and
by configuring the XT_SEL jumper, defined in Ta-
ble 1, to the appropriate position, as described be-
low.
XT_SEL Jumper and XT Clock Line
When the master clock for the board is derived
from methods (1), (2), or (3), the XT_SEL jumper
may be set to the XTAL position. This position
disconnects the XT clock line on the DSP port (Fig-
ure 9) from the XTI/XTO clock and crystal pins of
the CS4226 (Figure 7).
In case (3), the XT line can be set up to output the
XTO signal from the CS4226. This configuration
makes a buffered version of the crystal clock fre-
quency available on the DSP port. This is accom-
plished by setting XT_SEL to the XTOUT
position, and by configuring the bidirectional clock
lines, XT, SCLK, and LRCK, to be outputs. The PC
software can be used to set the DMS 1/0 bits in the
DSP Port Mode Byte to 01 or 10, making the clock
lines outputs on the CS4226. The PC software also
generates a control line called SP_BUF, which con-
trols the direction of the bidirectional transceiver,
U16 (Figure 8). Care must be taken to ensure that
the DMS bit settings correspond to the direction set
by the software control line. Details on the soft-
ware are given in the last section of this datasheet.
In case (4), the XT line can serve as the master
clock source for the CDB4226. To configure the
board in this manner, set the XT_SEL jumper to the
XTIN position. Additionally, the XT, SCLK, and
LRCK lines on the DSP port must be configured as
inputs to the evaluation board. The PC software is
used to set the DMS1/0 bits to 00 (LRCK and
SCLK are inputs). Also, the software is used to set
the direction of the bidirectional buffer, U16, so
that XT, SCLK, and LRCK are buffered onto the
board.
Notice that when XT is used as an external master
clock source for the board, the SCLK and LRCK lines
cannot be outputs. SCLK and LRCK must be sourced
externally.
DIGITAL INPUTS
The CS4226 can accept digital audio signals in ei-
ther serial form or S/PDIF form. The CS2/1/0 bits
in the Clock Mode Byte are used in conjunction with
the RX_SEL jumper (defined in Table 1) to config-
ure the board for serial or S/PDIF data sources.
Serial Input Interface
Serial data can be received through the AUX port
header, AUX_HDR (Figure 8), which provides ac-
cess to the AUX port of the CS4226. The four clock
and data lines on AUX_HDR are defined in Table
2. The CS4226 will accept serial data through the
AUX port by setting the CS2/1/0 bits in the Clock
Mode Byte to 0, 1, 2, or 3 (hex), and by moving the
RX_SEL jumper to the RX_AUXB position.
Notice that the LRCLKAUX and SCLKAUX lines
on the AUX port are bidirectional. The AMS1/0
bits in the Auxiliary Port Mode Byte determine the
direction of the LRCLKAUX and SCLKAUX
lines. The PC software generates a control line
called AUX_BUF, which controls the direction of
the bidirectional transceiver, U23 (Figure 8). Care
must be taken to ensure that the AMS bits corre-
spond to the direction set by the software control
line. Details on the software are given in the last
section of this datasheet.
A buffered version of CLKOUT, called
CLKOUT1, is available on AUX_HDR. CLKOUT
frequencies of 1 Fs, 256 Fs, 384 Fs, and 512 Fs can
be selected using the CO1/0 bits in the Clock Mode
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DS188DB1