CS4226 Datasheet, PDF (44/60 Pages) Cirrus Logic – Surround Sound Codec

CDB4226
DSP Port
Mode Byte
(hex)
1 = open, 0 = closed, X = don’t care, N/A = not available
Descriptor
DCK1-DCK0 = 00, 01, or 11 => 128, 48, or 64 bit clocks per Fs period.
01, 41, C1 CS4226 slave, valid data on SCLK rising edge, right-justified, 18 bit
02, 42, C2 CS4226 slave, valid data rising edge, right-justified, 16 bit
03, 43, C3 CS4226 slave, valid data rising edge, left-justified, 20 bit in, 24 bit out
04, 44, C4 CS4226 slave, valid data rising edge, I²S, 20 bit in, 24 bit out
09, 49, C9 CS4226 slave, valid data on SCLK falling edge, right-justified, 18 bit
0A, 4A, CA CS4226 slave, valid data falling edge, right-justified, 16 bit
0B, 4B, CB CS4226 slave, valid data falling edge, left-justified, 20 bit in, 24 bit out
0C, 4C, CC CS4226 slave, valid data falling edge, I²S, 20 bit in, 24 bit out
11, 51, D1 CS4226 master burst, valid data on SCLK rising edge, right-justified, 18 bit
12, 52, D2 CS4226 master burst, valid data rising edge, right-justified, 16 bit
13, 53, D3 CS4226 master burst, valid data rising edge, left-justified, 20 bit in, 24 bit out
14, 54, D4 CS4226 master burst, valid data rising edge, I²S, 20 bit in, 24 bit out
19, 59, D9 CS4226 master burst, valid data on SCLK falling edge, right-justified, 18 bit
1A, 5A, DA CS4226 master burst, valid data falling edge, right-justified, 16 bit
1B, 5B, DB CS4226 master burst, valid data falling edge, left-justified, 20 bit in, 24 bit out
1C, 5C, DC CS4226 master burst, valid data falling edge, I²S, 20 bit in, 24 bit out
21, E1
CS4226 master nonburst, valid data on SCLK rising edge, right-justified, 18 bit
22, E2
CS4226 master nonburst, valid data rising edge, right-justified, 16 bit
23, E3
24, E4
CS4226 master nonburst, valid data rising edge, left-justified, 20 bit in, 24 bit out
CS4226 master nonburst, valid data rising edge, I²S, 20 bit in, 24 bit out
29, E9
CS4226 master nonburst, valid data on SCLK falling edge, right-justified, 18 bit
2A, EA
CS4226 master nonburst, valid data falling edge, right-justified, 16 bit
2B, EB
2C, EC
CS4226 master nonburst, valid data falling edge, left-justified, 20 bit in, 24 bit out
CS4226 master nonburst, valid data falling edge, I²S, 20 bit in, 24 bit out
DCK1-DCK0 = 10 =>32 bit blocks per Fs period (all formats default to 16 bits)
80, 81, 82 CS4226 slave, valid data on SCLK rising edge, right-justified,16 bit
83
CS4226 slave, valid data rising edge, left-justified, 16 bit
84
CS4226 slave, valid data rising edge, I²S, 16 bit
88, 89, 8A CS4226 slave, valid data on SCLK falling edge, right-justified, 16 bit
8B
CS4226 slave, valid data falling edge, left-justified, 16 bit
8C
CS4226 slave, valid data falling edge, I²S, 16 bit
90, 91, 92 CS4226 master burst, valid data on SCLK rising edge, right-justified, 16 bit
93
CS4226 master burst, valid data rising edge, left-justified, 16 bit
94
CS4226 master burst, valid data rising edge, I²S, 16 bit
98, 99, 9A CS4226 master burst, valid data on SCLK falling edge, right-justified, 16 bit
9B
CS4226 master burst, valid data falling edge, left-justified, 16 bit
9C
CS4226 master burst, valid data falling edge, I²S, 16 bit
A0, A1, A2 CS4226 master nonburst, valid data on SCLK rising edge, right-justified, 16 bit
A3
CS4226 master nonburst, valid data rising edge, left-justified, 16 bit
A4
CS4226 master nonburst, valid data rising edge, I²S, 16 bit
A8, A9, AA CS4226 master nonburst, valid data on SCLK falling edge, right-justified, 16 bit
AB
CS4226 master nonburst, valid data falling edge, left-justified, 16 bit
AC
CS4226 master nonburst, valid data falling edge, I²S, 16 bit
SW1: #4
SP_RISING
SW1: #3
SP_L_RB
SW1:
#2, #1
BITS1/
BITS0
S2: #5
I²S
1
0
01
0
1
0
00
0
1
1
10
0
1
X
XX
1
0
0
01
0
0
0
00
0
0
1
10
0
0
X
XX
1
1
0
01
0
1
0
00
0
1
1
10
0
1
X
XX
1
0
0
01
0
0
0
00
0
0
1
10
0
0
X
XX
1
1
0
01
0
1
0
00
0
1
1
10
0
1
X
XX
1
0
0
01
0
0
0
00
0
0
1
10
0
0
X
XX
1
1
0
00
0
1
1
XX
0
1
X
XX
1
0
0
00
0
0
1
00
0
0
X
XX
1
1
0
00
0
1
1
00
0
1
X
XX
1
0
0
00
0
0
1
00
0
0
X
XX
1
1
0
00
0
1
1
00
0
1
X
XX
1
0
0
00
0
0
1
00
0
0
X
XX
1
Table 4. DSP Port Formats Supported by CS8402A Transmitter
44
DS188DB1