CS4226 Datasheet, PDF (17/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
successive reads or writes. If INCR is set to a 1,
then MAP will auto increment after each byte is
read or written, allowing block reads or writes of
successive registers.
To read a register, the MAP has to be set to the cor-
rect address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The auto MAP increment bit (INCR)
may be set or not, as desired. To begin a read, bring
CS low, send out the chip address and set the
read/write bit (R/W) high. The next falling edge of
CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data
is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 8. There is no CS pin. Pins AD0, AD1
form the partial chip address. The upper 5 bits of
the 7 bit address field must be 00100. To commu-
nicate with a CS4226, the LSBs of the chip address
field, which is the first byte sent to the CS4226,
should match the settings of the AD1, AD0 pins.
The eighth bit of the address bit is the R/W bit (high
for a read, low for a write). The next byte is the
Memory Address Pointer (MAP) which selects the
register to be read or written. If the operation is a
write, the next byte is the data to be written to the
register pointed to by the MAP. If the operation is
a read, the contents of the register pointed to by the
MAP will be output. Setting the auto increment bit
in MAP, allows successive reads or writes of con-
secutive registers. Each byte is separated by an ac-
knowledge bit. I²C bus is a registered trademark of
Philips Semiconductors.
Control Port Bit Definitions
All registers can be written and read back, except
the DAC Status Report Byte, ADC Status Report
Byte, Receiver Status Byte, and the Receiver Chan-
nel Status Bytes, which are read only. See the bit
definition tables for bit assignment information.
CS
CCLK
CHIP
ADDRESS
MAP
DATA
CDIN
0010000
R/W
MSB
LSB
byte 1 byte n
CHIP
ADDRESS
0010000 _R/W
CDOUT
MSB
LSB MSB
LSB
High Impedance
MAP = Memory Address Pointer
Figure 7. Control Port Timing, SPI mode
SDA
00100
ADDR
AD1-0
Note 1
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. Control Port Timing, I²C Mode
DS188F1
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