CS4226 Datasheet, PDF (12/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
The mute also takes effect on a zero-crossing or af-
ter a timeout. In addition, the CS4226 has an op-
tional mute on consecutive zeros feature, where all
DAC outputs will mute if they receive between 512
and 1024 consecutive zeros (or -1 code) on all six
channels. A single non-zero value will unmute the
DAC outputs. This feature can be disabled with the
MUTC bit in the DAC Control Byte. When using
the internal PLL as the clock source, all DACs will
instantly mute when the PLL detects an error.
Clock Generation
The master clock to operate the CS4226 may be
generated by using the on-chip inverter and an ex-
AOUT
11 kΩ
22 kΩ
3.9 kΩ
1000pF
CMOUT
5 kΩ
150pF
_
+
Example
Op-Amps
are
MC33078
0.47 µF
2-Pole Butterworth Filter
560 pF
5.85 kΩ
1.1 kΩ 4.75 kΩ
AOUT
1.21 kΩ
_
5600 pF
5600 pF ⁺
CMOUT
5 kΩ
0.47 µF
3-Pole Butterworth Filter
Figure 3.
ternal crystal, by using the on-chip PLL, or by us-
ing an external clock source. In all modes it is
required to have SCLK and LRCK synchronous to
the selected master clock.
Clock Source
The CS4226 requires a high frequency master
clock to run the internal logic. The Clock Source
bits, CS0/1/2 in Clock Mode Byte, determine the
source of the clock. A high frequency crystal can be
connected to XTI and XTO, or a high frequency
clock can be applied to XTI. In both these cases, the
internal PLL is disabled, and the VCO turns off.
The externally supplied high frequency clock can
be 256 Fs, 384 Fs or 512 Fs; this is set by the CI0/1
bits in the Clock Mode Byte. When using the on-
chip crystal oscillator, external loading capacitors
are required, see Figure 1. High frequency crystals
(>8MHz) should be parallel resonant, fundamental
mode and designed for 20 pF loading (equivalent to
40 pF to ground on each leg).
Alternatively, the on-chip PLL may be used to gen-
erate the required high frequency clock. The PLL
input clock is 1 Fs, and may be input from LRCK-
AUX, LRCK, or from XTI/XTO. In this last case,
a 1 Fs clock may be input into XTI, or a 1 Fs crystal
attached across XTI/XTO. When an external 1 Fs
crystal is attached, extra components will be re-
quired, see Figure 1. The PLL will lock onto a new
1 Fs clock in about 90 ms. If the PLL input clock is
removed, the VCO will drift to the low frequency
end of its frequency range.
The PLL can also be used to lock to an S/PDIF data
source on RX1, RX2, RX3, or RX4. Source selec-
tion is accomplished with the CS2/1/0 bits in the
Clock Mode Byte. The PLL will lock to an S/PDIF
source in about 90 ms.
Finally, the PLL has two filter loop current modes,
normal and high current, that are selected via the
LC bit in the Converter Control Byte. In the normal
mode, the loop current is 25 µA. In the high current
12
DS188F1