CS4226 Datasheet, PDF (13/60 Pages) Cirrus Logic – Surround Sound Codec

CS4226
mode, the loop current is 300 µA. The high current
mode allows the use of lower impedance filter
components which minimizes the influences of
board contamination. See the table in Figure 1 for
filter component values in each mode.
Master Clock Output
CLKOUT is a master clock output provided to al-
low synchronization of external components.
Available CLKOUT frequencies of 1 Fs, 256 Fs,
384 Fs, and 512 Fs, are selectable by the CO0/1
bits of the Clock Mode Byte.
Generation of CLKOUT for 384 Fs and 512 Fs is
accomplished with an on chip clock multiplier and
may contain clock jitter. The source of the 256 Fs
CLKOUT is the output of the PLL or a divided
down clock from the XTI/XTO input. If 384 Fs is
chosen as the input clock at XTI and 256 Fs is cho-
sen as the output, CLKOUT will have approxi-
mately a 33% duty cycle. In all other cases
CLKOUT will typically have a 50% duty cycle.
Synchronization
The DSP port and Auxiliary port must operate syn-
chronously to the CS4226 clock source. The serial
port will force a reset of the data paths in an attempt
to resynchronize if non-synchronous data is input
to the CS4226. It is advisable to mute the DACs
when changing from one clock source to another to
avoid the output of undesirable audio signals as the
CS4226 resynchronizes.
Digital Interfaces
There are 3 digital audio interface ports: the audio
DSP port, the auxiliary digital audio port, and the
S/PDIF reciever. The serial data is represented in
2’s complement format with the MSB-first in all
formats.
Audio DSP Serial Interface Signals
The serial interface clock, SCLK, is used for trans-
mitting and receiving audio data. The active edge
of SCLK is chosen by setting the DSCK bit in the
DSP Port Mode Byte. SCLK can be generated by
the CS4226 (master mode) or it can be input from
an external SCLK source (slave mode). Mode se-
lection is set with the DMS1/0 bits in the DSP Port
Mode Byte. The number of SCLK cycles in one
system sample period is programmable to be 32,
48, 64, or 128 by setting the DCK1/0 bits in the
DSP Port Mode Byte.
The Left/Right clock (LRCK) is used to indicate
left and right data and the start of a new sample pe-
riod. It may be output from the CS4226, or it may
be generated from an external controller. The fre-
quency of LRCK must be equal to the system sam-
ple rate, Fs.
SDIN1, SDIN2, and SDIN3 are the data input pins,
each of which drive a pair of DACs. SDOUT1 and
SDOUT2 can carry the output data from the two
20-bit ADC’s, the mono ADC, the auxiliary digital
audio port, and the S/PDIF receiver. Selection de-
pends on the IS1/0 bits in the ADC control byte.
The audio DSP port may also be configured so that
all 6 DAC’s data is input on SDIN1, and all 3
ADC’s data is output on SDOUT1. Table 3 outlines
the serial interface ports.
DAC Inputs
SDIN1
left channel
right channel
single line
SDIN2
left channel
right channel
SDIN3
left channel
right channel
DAC #1
DAC #2
All 6 DAC channels
DAC #3
DAC #4
DAC #5
DAC #6
Table 3. DSP Serial Interface Ports
Audio DSP Serial Interface Formats
The audio DSP port supports 7 alternate formats,
shown in Figures 4, 5, and 6. These formats are
chosen through the DSP Port Mode Byte with the
DDF2/1/0 bits.
Formats 5 and 6 are single line data modes where
all DAC channels are combined onto a single input
DS188F1
13