EP9312 Datasheet, PDF (60/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
Table T illustrates the pin signal multiplexing and configuration options.
Table T. Pin Multiplex Usage Information
Physical
Pin Name
COL[7:0]
ROW[7:0]
EGPIO[0]
EGPIO[1]
EGPIO[2]
EGPIO[3]
EGPIO[4]
EGPIO[5]
EGPIO[6]
EGPIO[7]
EGPIO[8]
EGPIO[9]
EGPIO[10]
EGPIO[11]
EGPIO[12]
EGPIO[13]
EGPIO[14]
EGPIO[15]
ABITCLK
ASYNC
ASDO
ASDI
ARSTn
SCLK1
SFRM1
SSPTX1
SSPRX1
IDEDA[2:0]
IDECS0n
IDECS1n
DIORn
DD[7:0]
DD[15:12]
SLA[1:0]
EEDAT
EECLK
Description
Multiplex signal name
GPIO
GPIO Port D[7:0]
GPIO
GPIO Port C[7:0]
Ring Indicator Input
RI
1Hz clock monitor
CLK1HZ
IDE DMA request
DMARQ
Transmit Enable output / HDLC clocks TENn / HDLCCLK1 / HDLCCLK3
I2S Transmit Data 1
SDO1
I2S Receive Data 1
SDI1
I2S Transmit Data 2
SDO2
DMA Request 0
DREQ0
DMA Acknowledge 0
DACK0
DMA EOT 0
DEOT0
DMA Request 1
DREQ1
DMA Acknowledge 1
DACK1
DMA EOT 1
DEOT1
I2S Receive Data 2
SDI2
PWM 1 output
PWMOUT1
IDE Device active / present
DASP
I2S Serial clock
SCLK
I2S Frame Clock
LRCK
I2S Transmit Data 0
SDO0
I2S Receive Data 0
SDI0
I2S Master clock
MCLK
I2S Serial clock
SCLK
I2S Frame Clock
LRCK
I2S Transmit Data 0
SDO0
I2S Receive Data 0
SDI0
GPIO
GPIO Port E[7:5]
GPIO
GPIO Port E[4]
GPIO
GPIO Port E[3]
GPIO
GPIO Port E[2]
GPIO
GPIO Port H[7:0]
GPIO
GPIO Port G[7:4]
GPIO
GPIO Port G[3:2]
GPIO
GPIO Port G[1]
GPIO
GPIO Port G[0]
60
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