EP9312 Datasheet, PDF (4/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
List of Figures
Figure 1. Timing Diagram Drawing Key ................................................................................. 14
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18
Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19
Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 21
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 22
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................ 23
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................ 24
Figure 12. Static Memory Burst Read Cycle Timing Measurement ....................................... 25
Figure 13. Static Memory Burst Write Cycle Timing Measurement ....................................... 26
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement ............................. 27
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement .............................. 28
Figure 16. Static Memory Turnaround Cycle Timing Measurement ....................................... 29
Figure 17. Register Transfer to/from Device .......................................................................... 31
Figure 18. PIO Data Transfer to/from Device ......................................................................... 33
Figure 19. Initiating an Ultra DMA data-in Burst ..................................................................... 35
Figure 20. Sustained Ultra DMA data-in Burst ....................................................................... 36
Figure 21. Host Pausing an Ultra DMA data-in Burst ............................................................. 36
Figure 22. Device Terminating an Ultra DMA data-in Burst ................................................... 37
Figure 23. Host Terminating an Ultra DMA data-in Burst ....................................................... 38
Figure 24. Initiating an Ultra DMA data-out Burst .................................................................. 39
Figure 25. Sustained Ultra DMA data-out Burst ..................................................................... 40
Figure 26. Device Pausing an Ultra DMA data-out Burst ....................................................... 40
Figure 27. Host Terminating an Ultra DMA data-out Burst .................................................... 41
Figure 28. Device Terminating an Ultra DMA data-out Burst ................................................. 42
Figure 29. Ethernet MAC Timing Measurement ..................................................................... 44
Figure 30. TI Single Transfer Timing Measurement ............................................................... 46
Figure 31. Microwire Frame Format, Single Transfer ............................................................ 46
Figure 32. SPI Format with SPH=1 Timing Measurement ..................................................... 47
Figure 33. Inter-IC Sound (I2S) Timing Measurement ........................................................... 48
Figure 34. AC ‘97 Configuration Timing Measurement .......................................................... 49
Figure 35. LCD Timing Measurement .................................................................................... 50
Figure 36. ADC Transfer Function ......................................................................................... 51
Figure 37. JTAG Timing Measurement .................................................................................. 52
Figure 38. 352 Pin PBGA Pin Diagram .................................................................................. 53
Figure 40. 352 PIN BGA PINOUT ................................................................................... 55
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