EP9312 Datasheet, PDF (15/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
SDCLK high time
SDCLK low time
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
Symbol
t_{clk_high}
t_{clk_low}
t_clkrf
t_d
t_h
t_DQd
t_DQh
t_DAs
t_DAh
Min
Typ
Max
-
(t_HCLK) / 2
-
-
(t_HCLK) / 2
-
-
2
4
-
-
8
1
-
-
-
-
8
1
-
-
2
-
-
3
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDRAM Load Mode Register Cycle
t_clkrf
SDCLK
t_d
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
t_{clk_low}
t_{clk_high}
t_h
OP-Code
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
DS515PP7
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