EP9312 Datasheet, PDF (59/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
.
Table S. Pin Descriptions
Pin Name
TCK
TDI
TDO
TMS
TRSTn
BOOT[1:0]
XTALI
XTALO
VDD_PLL
GND_PLL
RTCXTALI
RTCXTALO
WRn
RDn
WAITn
AD[25:0]
DA[31:0]
CSn[3:0]
CSn[7:6]
DQMn[3:0]
SDCLK
SDCLKEN
SDCSn[3:0]
RASn
CASn
SDWEn
P[17:0]
SPCLK
HSYNC
V_CSYNC
BLANK
BRIGHT
PWMOUT
Xp, Xm
Yp, Ym
sXp, sXm
sYp, sYm
VDD_ADC
GND_ADC
COL[7:0]
ROW[7:0]
USBp[2:0]
USBm[2:0]
TXD0
RXD0
CTSn
DSRn
DTRn
Block
JTAG
JTAG
JTAG
JTAG
JTAG
System
PLL
PLL
PLL
PLL
RTC
RTC
PBUS
PBUS
PBUS
PBUS
PBUS
PBUS
PBUS
PBUS
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Raster
Raster
Raster
Raster
Raster
Raster
PWM
ADC
ADC
ADC
ADC
ADC
ADC
Key
Key
USB
USB
UART1
UART1
UART1
UART1
UART1
Pad Pull
Type Type
Description
I
I
4ma
I
I
I
A
A
P
G
A
A
4ma
4ma
I
8ma
8ma
4ma
4ma
8ma
8ma
8ma
4ma
8ma
8ma
8ma
4ma
12ma
8ma
8ma
8ma
4ma
8ma
A
A
A
A
P
G
8ma
8ma
A
A
4ma
I
I
I
4ma
PD JTAG clock in
PD JTAG data in
JTAG data out
PD JTAG test mode select
PD JTAG reset
PD Boot mode select in
Main oscillator input
Main oscillator output
Main oscillator power, 1.8V
Main oscillator ground
RTC oscillator input
RTC oscillator output
SRAM Write strobe out
SRAM Read / OE strobe out
PU SRAM Wait in
Shared Address bus out
PU Shared Data bus in/out
PU Chip select out
PU Chip select out
Shared data mask out
SDRAM clock out
SDRAM clock enable out
SDRAM chip selects out
SDRAM RAS out
SDRAM CAS out
SDRAM write enable out
PU Pixel data bus out
PU Pixel clock in/out
PU Horizontal synchronization / line pulse out
PU
Vertical or composite synchronization / frame
pulse out
PU Composite blanking signal out
PWM brightness control out
Pulse width modulator output
Touchscreen ADC X axis
Touchscreen ADC Y axis
Touchscreen ADC X axis feedback
Touchscreen ADC Y axis feedback
Touchscreen ADC power, 3.3V
Touchscreen ADC ground
PU Key matrix column inputs
PU Key matrix row outputs
USB positive signals
USB negative signals
Transmit out
PU Receive in
PU Clear to send / transmit enable
PU Data set ready / Data Carrier Detect
Data Terminal Ready output
Table S. Pin Descriptions (Continued)
Pin Name
Block
Pad Pull
Type Type
Description
RTSn
TXD1
RXD1
TXD2
RXD2
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
GRLED
RDLED
EECLK
EEDAT
ABITCLK
ASYNC
ASDI
ASDO
ARSTn
SCLK1
SFRM1
SSPRX1
SSPTX1
INT[3:0]
PRSTn
RSTOn
SLA[1:0]
EGPIO[15:0]
DD[15:8]
DD7
DD[6:0]
IDEDA[2:0]
IDECS0n
IDECS1n
DIORn
DIOWn
DMACKn
IORDY
CVDD
RVDD
CGND
RGND
UART1 4ma
Ready to send
UART2 4ma
Transmit / IrDA output
UART2
I
PU Receive / IrDA input
UART3 4ma
Transmit
UART3
I
PU Receive
EMAC 4ma
Management data clock
EMAC 4ma PU Management data input/output
EMAC
I
PD Receive clock in
EMAC
I
PD Receive data in
EMAC
I
PD Receive data valid
EMAC
I
PD Receive data error
EMAC 4ma PU Transmit clock in
EMAC
I
PD Transmit data out
EMAC 4ma PD Transmit enable
EMAC 4ma PD Transmit error
EMAC
I
PD Carrier sense
EMAC
I
PU Collision detect
LED
12ma
Green LED
LED
12ma
Red LED
EEPROM 4ma PU EEPROM / Two-wire Interface clock
EEPROM 4ma PU EEPROM / Two-wire Interface data
AC97
8ma PD AC97 bit clock
AC97
8ma PD AC97 frame sync
AC97
I
PD AC97 Primary input
AC97
8ma PU AC97 output
AC97
8ma
AC97 reset
SPI1
8ma PD SPI bit clock
SPI1
8ma PD SPI Frame Clock
SPI1
I
PD SPI input
SPI1
8ma
SPI output
INT
I
PD External interrupts
Syscon
I
PU Power on reset
Syscon 4ma
User Reset in out - open drain
EEPROM 4ma
Flash programming voltage control
GPIO I/O, 4ma PU Enhanced GPIO
IDE
8ma PU IDE data bus
IDE
8ma PD IDE data bus
IDE
8ma PU IDE data bus
IDE
8ma
IDE Device address output
IDE
8ma
IDE Chip Select 0 output
IDE
8ma
IDE Chip Select 1 output
IDE
8ma
IDE Read strobe output
IDE
8ma
IDE Write strobe output
IDE
8ma
IDE DMA acknowledge output
IDE
I
PU IDE ready input
Power
P
Digital power, 1.8V
Power
P
Digital power, 3.3V
Ground
G
Digital ground
Ground
G
Digital ground
DS515PP7
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