EP9312 Datasheet, PDF (56/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
Pin List
The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball.
Ball
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
Signal
CSN[7]
DA[28]
AD[18]
DD[8]
DD[4]
AD[17]
RDN
RXCLK
MIIRXD[0]
RXDVAL
MIITXD[2]
TXERR
CLD
NC
NC
NC
EGPIO[12]
EGPIO[15]
NC
NC
CSN[2]
DA[31]
DA[30]
DA[27]
DD[7]
DD[3]
WRN
MDIO
MIIRXD[1]
RXERR
MIITXD[1]
CRS
NC
NC
NC
NC
EGPIO[13]
NC
WAITN
TRSTN
CSN[1]
CSN[3]
Ball
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F1
F2
F3
F4
F5
F6
F7
F14
F15
F16
F17
F18
F19
F20
G1
G2
G3
G4
G5
G6
G15
G16
G17
G18
G19
G20
H1
H2
H3
H4
Signal
RVDD
GND
GND
RVDD
CVDD
CVDD
GND
ASDI
DIOWN
EGPIO[0]
EGPIO[3]
EGPIO[5]
SDCSN[3]
DA[22]
DA[24]
AD[25]
RVDD
GND
CVDD
CVDD
GND
GND
EGPIO[2]
EGPIO[4]
EGPIO[6]
EGPIO[8]
SDCSN[0]
SDCSN[1]
SDWEN
SDCLK
RVDD
RVDD
RVDD
RVDD
EGPIO[7]
EGPIO[9]
EGPIO[10]
EGPIO[11]
DQMN[3]
CASN
RASN
SDCSN[2]
Ball
L3
L4
L5
L8
L9
L10
L11
L12
L13
L16
L17
L18
L19
L20
M1
M2
M3
M4
M5
M8
M9
M10
M11
M12
M13
M16
M17
M18
M19
M20
N1
N2
N3
N4
N5
N6
N8
N9
N10
N11
N12
N13
Signal
DA[16]
DA[15]
GND
GND
GND
GND
GND
GND
GND
CVDD
COL[5]
COL[7]
RSTON
PRSTN
AD[7]
DA[14]
AD[6]
AD[5]
CVDD
GND
GND
GND
GND
GND
GND
GND
COL[4]
COL[3]
COL[6]
CSN[0]
DA[13]
DA[12]
DA[11]
AD[3]
CVDD
CVDD
GND
GND
GND
GND
GND
GND
Ball
T13
T14
T15
T16
T17
T18
T19
T20
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
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©Copyright 2005 Cirrus Logic (All Rights Reserved)
Signal
CVDD
GND
INT[0]
USBM[1]
RXD[0]
TXD[2]
ROW[2]
ROW[4]
AD[0]
P[15]
P[10]
P[7]
P[6]
P[4]
P[0]
AD[13]
DA[3]
DA[0]
DSRN
BOOT[1]
NC
SSPRX1
INT[1]
PWMOUT
USBM[0]
RXD[1]
TXD[1]
ROW[1]
P[16]
P[11]
P[8]
DD[15]
DD[13]
P[1]
AD[14]
AD[12]
DA[2]
IDECS0N
IDEDA[2]
TDI
GND
ASYNC
DS515PP7