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| DAC8560 Datasheet, PDF (6/29 Pages) Burr-Brown (TI) – 16-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference | |||
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DAC8560
SLAS464 â DECEMBER 2006
SERIAL WRITE OPERATION
SCLK
SYNC
DIN
1
t8
t4
t1
t9
24
t3
t2
t7
DB23
t6
t5
t10
DB0
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DB23
TIMING REQUIREMENTS(1)(2)
VDD = 2.7V to 5.5V, all specifications â40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t1(3) SCLK cycle time
t2 SCLK HIGH time
t3 SCLK LOW time
t4 SYNC to SCLK rising edge setup time
t5 Data setup time
t6 Data hold time
t7 SCLK falling edge to SYNC rising edge
t8 Minimum SYNC HIGH time
t9 24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
MIN TYP MAX UNIT
50
ns
33
13
ns
13
22.5
ns
13
0
ns
0
5
ns
5
4.5
ns
4.5
0
ns
0
50
ns
33
100
ns
100
15
ns
15
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
6
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