DAC8560 Datasheet, PDF (24/29 Pages) Burr-Brown (TI) – 16-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8560
SLAS464 – DECEMBER 2006
MICROPROCESSOR INTERFACING
DAC8560 TO 8051 Interface
See Figure 71 for a serial interface between the
DAC8560 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8560, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data is to be transmitted to the DAC8560,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken HIGH following
the completion of the third write cycle. The 8051
outputs the serial data in a format which has the LSB
first. The DAC8560 requires its data with the MSB as
the first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
80C51/80L51⁽¹⁾
P3.3
TXD
RXD
DAC8560 ⁽¹⁾
SYNC
SCLK
D_IN
NOTE: (1) Additional pins omitted for clarity.
Figure 71. DAC8560 to 80C51/80L51 Interface
DAC8560 to Microwire Interface
Figure 72 shows an interface between the DAC8560
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8560 on the rising edge of
the SK signal.
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Microwire^TM
CS
SK
SO
NOTE: (1) Additional pins omitted for clarity.
DAC8560⁽¹⁾
SYNC
SCLK
D_IN
Figure 72. DAC8560 to Microwire Interface
DAC8560 to 68HC11 Interface
Figure 73 shows a serial interface between the
DAC8560 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8560, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11⁽¹⁾
PC7
SCK
MOSI
NOTE: (1) Additional pins omitted for clarity.
DAC8560 ⁽¹⁾
SYNC
SCLK
D_IN
Figure 73. DAC8560 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8560,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
operation is performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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