DAC8560 Datasheet, PDF(19/29 Page) Burr-Brown (TI) – 16-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

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DAC8560 Datasheet, PDF (19/29 Pages) Burr-Brown (TI) – 16-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

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DAC8560

www.ti.com

SLAS464 â DECEMBER 2006

INTERNAL REFERENCE

The DAC8560 includes a 2.5V internal reference that

is enabled by default. The internal reference is

externally available at the VREF pin. A minimum

100nF capacitor is recommended between the

reference output and GND for noise filtering.

The internal reference of the DAC8560 is a bipolar

transistor-based, precision bandgap voltage

reference. The basic bandgap topology is shown in

Figure 64. Transistors Q1 and Q2 are biased such

that the current density of Q1 is greater than that of

Q2. The difference of the two base-emitter voltages

(VBE1 - VBE2) has a positive temperature coefficient

and is forced across resistor R1. This voltage is

gained up and added to the base-emitter voltage of

Q2, which has a negative temperature coefficient.

The resulting output voltage is virtually independent

of temperature. The short-circuit current is limited by

design to approximately 100mA.

VREF

Reference

Disable

Figure 64. Simplified Schematic of the Bandgap

Reference

Enable/Disable Internal Reference

The DAC8560 internal reference is enabled by

default; however, the reference can be disabled for

debugging or evaluation purposes. A serial

command requiring at least two additional SCLK

cycles at the end of the 24-bit write sequence (see

Serial Interface section) must be used to disable the

internal reference. For proper operation, a total of at

least 26 SCLK cycles are required for each

enable/disable internal reference update sequence,

during which SYNC must be held low. To disable the

internal reference, execute the write sequence

illustrated in Table 1 followed by at least two

additional SCLK falling edges while SYNC is low.

To then enable the reference, either perform a

power-cycle to reset the device, or sequentially

execute the two write sequences in Table 2 and

Table 3. Each of these write sequences must be

followed by at least two additional SCLK falling

edges while SYNC remains low.

During the time that the internal reference is

disabled, the DAC will function normally using an

external reference. At this point, the internal

reference is disconnected from the VREF pin

(tri-state). Do not attempt to drive the VREF pin

externally and internally at the same time indefinitely.

Table 1. Write Sequence for Disabling the DAC8560 Internal Reference

DB23

DB0

010010000000010000000001

Table 2. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)

DB23

DB0

010011000000010000000000

Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)

DB23

DB0

010010010000010000000001

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