CS4281 Datasheet, PDF (19/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
ISA Interrupt Select Register (IISR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VAUXS VAC2 VAC1 VAC0 AUXP BCF2 BCF1 BCF0 GTD
IRQC3 IRQC2 IRQC1 IRQC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQB3 IRQB2 IRQB1 IRQB0
IRQA3 IRQA2 IRQA1 IRQA0
Address: PCI CFG: F4h, Read-Write if CWPR configured, otherwise Read-Only
Definition: Defines the ISA interrupt associated with a particular pin and relays flags from BIOS to the OS and
host software. This register is unaffected by the PCI RST# signal.
Bit Descriptions:
VAUXS
Vaux Support. This bit is reflected into the D3_cold support bit, PMC.PMD3C. BIOS code would
generally set this bit if VAUX is supported.
VAC[2:0]
Vaux Current. These bits are reflected in the PMC.VAC[2:0] bits and must be initialized by the
BIOS to indicate how much current Vaux pulls. Note this is total current and is the combined
CS4281 and any attached Codecs and external logic using Vaux.
000 - 0 mA (self powered/don’t support Vaux)
001 - 55 mA
010 - 100 mA
011 - 160 mA
100 - 220 mA
101 - 270 mA
110 - 320 mA
111 - 375 mA (spec maximum)
AUXP
Auxiliary Power. This bit is reflected in the PMC.AUXP bit.
BCF[2:0] BIOS Configuration Flags. These bits have no direct affect on the operation of the CS4281 and
may be used by host software when communicating with the BIOS.
GTD
Global Trapping Disable. When set, disables all I/O trapping. When GTD is clear, I/O trapping
is allowed (must be configured through other registers).
IRQA[3:0] IRQA pin interrupt mapping. A 0 disables (high impedance) the corresponding ISA interrupt
pin. A non-zero value (preferably the actual ISA interrupt connected to the pin) allows the pin
to be enabled through software drivers.
IRQB[3:0] IRQB pin interrupt mapping. A 0 disables (high impedance) the corresponding ISA interrupt
pin. A non-zero value (preferably the actual ISA interrupt connected to the pin) allows the pin
to be enabled through software drivers.
IRQC[3:0] IRQC pin interrupt mapping. A 0 disables (high impedance) the corresponding ISA interrupt
pin. A non-zero value (preferably the actual ISA interrupt connected to the pin) allows the pin
to be enabled through software drivers.
CIRRUS LOGIC PRODUCT DATA SHEET
DS308PP4
19