CS4281 Datasheet, PDF (12/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
PCI Bus Transactions
As a target of a PCI bus transaction, the CS4281 supports the Memory Read (from internal registers or
memory), Memory Write (to internal registers or memory), Configuration Read (from CS4281 configura-
tion registers), Configuration Write (to CS4281 configuration registers), Memory Read Multiple (aliased
to Memory Read), Memory Read Line (aliased to Memory Read), and the Memory Write and Invalidate
(aliased to Memory Write) transfer cycles. The I/O Read, I/O Write, Interrupt Acknowledge, Special Cy-
cles, and Dual Address Cycle transactions are not supported.
As a Bus Master, the CS4281 generates the Memory Read and Memory Write transactions. The Memory
Read, Configuration Read, Configuration Write, Memory Read Line, Memory Write and Invalidate, I/O
Read, I/O Write, Interrupt Acknowledge, Special Cycles, and Dual Address Cycle transactions are not
generated.
The PCI bus transactions supported by the
CS4281 device are summarized in Table 1. Note ^Initiator
Target
Type
PCI Dir
that no Target Abort conditions are signalled by _Host
the device. Byte, word, and doubleword transfers
are supported for Configuration Space accesses. ^Host
Registers (BA0) Mem Write In
Registers (BA0) Mem Read Out
Only doubleword transfers are supported for Reg- Host Memories (BA1) Mem Write In
ister and Memory area accesses. Bursting is not _Host
supported for host-initiated transfers to/from the
CS4281 internal register space, RAM memory ^Host
Memories (BA1) Mem Read Out
Config Space 1 Config Write In
space, or PCI configuration space (disconnect af- Host Config Space 1 Config Read Out
ter first phase of transaction is completed).
DMA
Host System
Mem Write Out
Configuration Space
DMA
Host System
Mem Read In
The content and format of the PCI Configuration
Space is given in Table 2. The registers from 00 to
Table 1. PCI Interface Transaction Summary
44h are standard PCI configuration registers. The registers from E0h to FFh are Cirrus-Logic specific and
are read-only by default. For protection from inadvertent writes, the Configuration Space registers from
E4h to FFh are read-only unless the CWPR register at E0h is loaded with 4281h. Once CWPR contains
4281h, the registers are writable.
Subsystem Vendor ID Fields
The Subsystem ID and Subsystem Vendor ID fields can be loaded in two ways. Typically add-in cards use
an external EEPROM where the CS4281 loads the data from EEPROM on power-up. For mother-board
systems the BIOS typically loads the Configuration Space at offset FCh (see Table 2). Once these values
are loaded they will appear in the Configuration Space offset 2Ch. The Subsystem ID and Subsystem Ven-
dor ID fields in the PCI Configuration Space default to value 0000h. The CWPR register at E0h must be
loaded with 4281h on order to write the Subsystem IDs at FCh.
CIRRUS LOGIC PRODUCT DATA SHEET
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DS308PP4