CS4281 Datasheet, PDF (15/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
Cirrus-Specific Configuration Registers
Configuration Space locations E0h through FFh are Cirrus-specific registers and are only listed in the PCI
specification as vendor-defined. E0h is the Configuration Write Protect register (CWPR) and blocks reg-
isters E4h through FFh from being written (they are read-only), when the CWPR register is anything but
4281h. When CWPR is programmed for 4281h, registers E4h through FFh are writable. This section will
describe the Cirrus-specific Configuration registers with the exception of the Subsystem ID register at FCh
which was described in the last section.
The Cirrus-specific registers provide the BIOS with access to general setup and configuration options of
the CS4281. Placing these registers in the Configuration Space lets the BIOS configure the CS4281 before
any operating system has assigned memory base addresses. Some general-purpose bits are also available
to allow the BOIS to communicate with the CS4281 driver software. Cirrus Logic must be contacted before
using any of these general-purpose bits when using Cirrus-supplied software drivers.
General Purpose I/O Register (GPIOR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GP3W GP3ST GP3PT GP3OE GP1W GP1ST GP1PT GP1OE VUPW VUPST VUPPO VUPLT VDNW VDNST VDNPO VDNLT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP3D GP1D
GPPS GPSS GP3S GP1S VUPS VDNS
Address: PCI CFG: E8h, Read-Write if CWPR configured, otherwise Read-Only
Definition: The General Purpose I/O register provides a host port for accessing extended general-purpose I/O
pins.
Bit Descriptions:
VDNS
VOLDN input Status: This bit reflects the status of the VOLDN input pin. If configured as sticky
(VDNST=1), VDNS reads one when the VOLDN pin goes active (edge sensitive - edge
defined by polarity bit VDNPO), and is cleared by writing a 0 to VDNS.
If configured as level sensitive (VDNST=0), this bit reflects the current state of the VOLDN pin
qualified by the polarity bit VDNPO.
VUPS
VOLUP input Status: This bit reflects the status of the VOLUP input pin. If configured as sticky
(VUPST=1), VUPS reads one when the VOLUP pin goes active (edge sensitive - edge defined
by polarity bit VUPPO), and is cleared by writing a 0 to VUPS.
If configured as level sensitive (VUPST=0), this bit reflects the current state of the VOLUP pin
qualified by the polarity bit VUPPO.
GP1S
ASDIN2/GPIO1 input Status: Assuming this pin is not configured for ASDIN2, this bit reflects
the status of the ASDIN2/GPIO1 pin. If ASDIN2/GPIO1 is an output, this bit reflects the actual
state of the pin. If ASDIN2/GPIO1 is an input:
If configured as sticky (GP1ST=1), this bit reads one when the ASDIN2/GPIO1 pin goes active
(edge sensitive - edge defined by polarity bit GP1PT), and is cleared by writing a 0 to GP1S.
If configured as level sensitive (GP1ST=0), this bit reflects the current state of the
ASDIN2/GPIO1 pin qualified by the polarity bit GP1PT.
See the Serial Port Power Management Control (SPMC) register description of ASDI2E bit.
GP3S
GPIO3 input Status: This bit reflects the status of the GPIO3 pin itself. If GPIO3 is an output,
this bit reflects the actual state of the pin. If GPIO3 is an input:
If configured as sticky (GP3ST=1), this bit reads one when the GPIO3 pin goes active (edge
sensitive - edge defined by polarity bit GP3PT), and is cleared by writing a 0 to GP3S.
If configured as level sensitive (GP3ST=0), this bit reflects the current state of the GPIO3 pin
qualified by the polarity bit GP3PT.
CIRRUS LOGIC PRODUCT DATA SHEET
DS308PP4
15