SAM9263_14 Datasheet, PDF (983/1024 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

47.10.3 MCI
The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data bus, and
internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full),
FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 47-13. MCI Timing Diagram
1
Bus Clock
CMD_DAT Input
2
Valid Data
CMD_DAT Output
6
Valid Data
4
3
Valid Data
Valid Data
5
Table 47-38. MCI Timings
Symbol
Parameter
Min
Max
1
1/t_CLK = CLK frequency at Data transfer Mode (PP)
0
51
2
Input hold time
1.5
3
Input setup time
-0.1
4
Output hold time
-1.0
5
Output setup time
1/t_CLK - 2.8
Units
MHz
ns
ns
ns
ns
SAM9263 [DATASHEET]
6249L–ATARM–28-Jun-13
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