SAM9263_14 Datasheet, PDF (796/1024 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

43.2 Block Diagram
Figure 43-1. Block Diagram
Atmel Bridge
APB
to
MCU
Bus
MCK
U
s
UDPCK
e
r
I
n
t
e
r
f
udp_int
a
c
e
external_resume
USB Device
W
W
r
Dual
r
a
Port
a
Serial
Interface
p
RAM
p
Engine
p
p
e
r
FIFO
e
r ^{12 MHz}
SIE
Master Clock
Domain
Suspend/Resume Logic
Recovered 12 MHz
Domain
txoen
eopn
txd
DP
Embedded
rxdm
USB
Transceiver
DM
rxd
rxdp
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit
values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz
clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then
notified that the device asks for a resume. This optional feature must be also negotiated with the host during the
enumeration.
SAM9263 [DATASHEET]
6249L–ATARM–28-Jun-13
796