SAM9263_14 Datasheet, PDF (306/1024 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

25.4.19 Single Destination Transaction Request Register
Name:
DMAC_SglReqDstReg
Address: 0x00800380
Access:
Read-write
Reset:
0x0
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
–
–
–
–
–
7
6
5
4
3
–
–
–
–
–
26
25
24
–
–
–
18
17
16
–
–
–
10
9
8
–
REQ_WE1
REQ_WE0
2
1
0
–
D_SG_REQ1 D_SG_REQ0
A bit is assigned for each channel in this register. DMAC_SglReqDstReg[n] is ignored when software handshaking is not enabled
for the source of channel n.
A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the
same AMBA write transfer.
• D_SG_REQx: Destination Single Request
• REQ_WEx: Request Write Enable
0 = Write disabled
1 = Write enabled
SAM9263 [DATASHEET]
6249L–ATARM–28-Jun-13
306