SAM9263_14 Datasheet, PDF (835/1024 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

Figure 44-2. Datapath Structure
Input Interface
FIFO
Serializer
Palette
Dithering
Configuration IF
Control Interface
Output
Shifter
Output Interface
This module transforms the data read from the memory into a format according to the LCD module used. It has four
different interfaces: the input interface, the output interface, the configuration interface and the control interface.
z The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus and
two push lines that are used by the DMA controller to fill the FIFOs.
z The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used (TFT
or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
z The configuration interface connects the datapath with the configuration block. It is used to select between the
different datapath configurations.
z The control interface connects the datapath with the timing generation block. The main control signal is the data-
request signal, used by the timing generation module to request new data from the datapath.
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter initial_latency
is defined as the number of LCDC Core Clock cycles until the first data is available at the output of the datapath. The
parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two consecutive data at the
output interface.
SAM9263 [DATASHEET]
6249L–ATARM–28-Jun-13
835