SAM9263_14 Datasheet, PDF (275/1024 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

25.3.5.6 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear regis-
ters: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading
the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.
3. Program the following channel registers:
1. Write the starting source address in the DMAC_SARx register for channel x.
2. Write the starting destination address in the DMAC_DARx register for channel x.
3. Program DMAC_CTLx and DMAC_CFGx according to Row 3 as shown in Table 25-2 on page 261. Pro-
gram the DMAC_LLPx register with ‘0’.
4. Write the control information for the DMA transfer in the DMAC_CTLx register for channel x. For example, in
this register, you can program the following:
z i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the TT_FC of the DMAC_CTLx register.
z ii. Set up the transfer characteristics, such as:
z Transfer width for the source in the SRC_TR_WIDTH field.
z Transfer width for the destination in the DST_TR_WIDTH field.
z Source master layer in the SMS field where source resides.
z Destination master layer in the DMS field where destination resides.
z Incrementing/decrementing or fixed address for source in SINC field.
z Incrementing/decrementing or fixed address for destination in DINC field.
5. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel
x.
6. If scatter is enabled (DMAC_CTLx.D_SCAT_EN), program the DMAC_DSRx register for channel x.
7. Write the channel configuration information into the DMAC_CFGx register for channel x.
z i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the
HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface
to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software
handshaking interface to handle source/destination requests.
z ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign
handshaking interface to the source and destination peripheral. This requires programming the SRC_PER
and DEST_PER bits, respectively.
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled.
5. Source and destination request single and burst DMAC transactions to transfer the block of data (assuming non-
memory peripherals). The DMAC acknowledges at the completion of every transaction (burst and single) in the
block and carries out the block transfer.
6. When the block transfer has completed, the DMAC reloads the DMAC_SARx register. The DMAC_DARx register
remains unchanged. Hardware sets the block complete interrupt. The DMAC then samples the row number as
shown in Table 25-2 on page 261. If the DMAC is in Row 1, then the DMA transfer has completed. Hardware sets
the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or
Transfer Complete interrupts, or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
SAM9263 [DATASHEET]
6249L–ATARM–28-Jun-13
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