AT697F Datasheet, PDF (98/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

Table 65. Timer 2 Control Register - TIMCTR2
Address = 0x80000058
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Bit Number
2
1
0
Mnemonic
ld2
rl2
en2
r/w
xxxx xxxx xxxx xxxx xxxx xxxx xxxx x
r/w
0x0
Description
Load counter
when written with ‘one’, will load the timer reload register into the timer counter register. Always reads as a
‘zero’.
Reload counter
If rl2 is set, then the counter will automatically be reloaded with the reload value after each underflow.
Enable counter
enables the timer when set.
Table 66. Prescaler Counter Register - SCAC
Address = 0x80000060
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
counter value [9:0]
Bit Number
9..0
r/w
xxxx xxxx xxxx xxxx xxxx xxx
Mnemonic Description
counter value[9:0] prescaler counter value
A read access gives the decounting value of the prescaler.
r/w
00 0000 0000
Table 67. Prescaler Reload Register - SCAR
Address = 0x80000064
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reload value [9:0]
Bit Number
9..0
r/w
xxxx xxxx xxxx xxxx xxxx xxx
r/w
00 0000 0000
Mnemonic Description
reload value [9:0] Prescaler reload value
A write access programs the reload value of the prescaler.
A read access gives the reload value of the prescaler.
Note: The reset value for SCAR is 0. This is not a legal value, it is however equivalent to a value of 3
and leads to a division rate of 4.
98 _{AT697F ADVANCE INFORMATION}
7703C–AERO–6/09