AT697F Datasheet, PDF (23/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697F ADVANCE INFORMATION
Asynchronous
Traps / Interrupts
The AT697F handles up to 15 interrupts. The interrupt controller is used to prioritize and propa-
gate interrupts requests from internal or external devices to the integer unit.
Figure 7. Interrupt Controller Block Diagram
PIO[15:0]
Interrupt Sources
Internal Interrupt
(Timer1, Uart1,...)
I/O Interrupt Reg.
IOIT1
IOIT2
Interrupt Clear Reg.
ITC
Interrupt Pending Reg.
ITP
Interrupt Force Reg.
ITF
mask
priority
trap1x generation
Interrupt Mask & Priority Reg.
ITMP
Operation
Interrupt List
When an interrupt is generated, the corresponding bit is set in the interrupt pending register
(ITP). The pending bits are ANDed with the interrupt mask register and then forwarded to the pri-
ority selector. The highest interrupt from priority level 1 will be forwarded to the IU - if no
unmasked pending interrupt exists on priority level 1, then the highest unmasked interrupt from
priority level 0 is forwarded.
When the IU acknowledges the interrupt, the corresponding pending bit will automatically be
cleared.
Interrupt can also be forced by setting a bit in the interrupt force register. In this case, the IU
acknowledgement will clear the force bit rather than the pending bit.
After reset, the interrupt mask register is set to all zeros while the remaining control registers are
undefined.
The following table presents the assignement of the interrupts.
Table 9. Interrupt Overview
Interrupt
TT (Trap Type)
15
0x1F
14
0x1E
13
0x1D
12
0x1C
11
0x1B
10
0x1A
9
0x19
8
0x18
7
0x17
6
0x16
5
0x15
4
0x14
3
0x13
Source
I/O interrupt [7]
PCI
I/O interrupt [6]
I/O interrupt [5]
DSU trace buffer
I/O interrupt [4]
Timer 2
Timer 1
I/O interrupt [3]
I/O interrupt [2]
I/O interrupt [1]
I/O interrupt [0]
UART 1
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