AT697F Datasheet, PDF (118/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

Table 106. PCI Target Status-Command Register - PCITSC
Address = 0x80000160
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
tms[3:0]
Bit Number
8
7
6
5
4
3..0
Mnemonic
frty
errmem
xff
xfe
rfe
tms[3:0]
r/w
0x0000 00
r/w r/w r/w r/w r/w
00011
Description
Force Retry
Set automatically during long delayed read to prevent the read from being overwritten
(Debug Purpose only)
Cleared by writing a 1.
Reception Fifo parity error
‘0’ = Do not save data with parity error
‘1’ = Data with parity error is saved to memory
TXMT Fifo full
‘1’ = force transmistion to abort
TXMT Fifo empty
‘1’ = flushes TXMT Fifo
TRCV Fifo empty
‘1’ = flushes TRCV Fifo
Target AHB master state
‘1111’ = reset the state machine
r/w
0000
Table 107. PCI Interrupt Enable Register - PCIITE
Address = 0x80000164
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Bit Number
7
6
5
4
3
Mnemonic
dmaer
imier
cmfer
imper
tier
r/w
0x0000 00
Description
DMA end of transfer
‘0’ = disable
‘1’ = enable
Initiator error
‘0’ = disable
‘1’ = enable
PCI core error
‘0’ = disable
‘1’ = enable
Initiator Parity error
‘0’ = disable
‘1’ = enable
Target error
‘0’ = disable
‘1’ = enable
r/w r/w r/w r/w r/w r/w r/w r/w
00000000
118 _{AT697F ADVANCE INFORMATION}
7703C–AERO–6/09