AT697F Datasheet, PDF (22/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

Traps Description
• reset - A reset trap is caused by an external reset request. It causes the processor to begin
executing at virtual address 0. After a Reset Trap, no special memory states are defined
exept the bits PSRJET’ and PSRJS that are initialized respectively ‘0’ and ‘1’.
• write error - An error exception occurred on a data store to memory.
• instruction_access_exception - A blocking error exception occurred on an instruction
access.
• illegal_instruction - An attempt was made to execute an instruction with an unimplemented
opcode, or an UNIMP instruction, or an instruction that would result in illegal processor
state.
• privileged_instruction - An attempt was made to execute a privileged instruction while
supervisor bit PSRJS is ‘0’ (not in supervisor mode).
• fp_disabled - An attempt was made to execute an FPU instruction while FPU is not enabled
or not present.
• cp_disabled - An attempt was made to execute a co-processor instruction while co-
processor is not enabled or not present.
• watchpoint_detected - An instruction fetch memory address or load/store data memory
address matched the contents of a pre-loaded implementation-dependent “watchpoint”
register.
• window_overflow - A SAVE instruction attempted to cause the current window pointer
(CWP) to point to an invalid window in the WIM.
• window_underflow - A RESTORE or RETT instruction attempted to cause the current
window pointer (CWP) to point to an invalid window in the WIM.
• register_hardware_error - An error exception occurred on a read only register access.
A register file uncorrectable error was detected.
• mem_address_not_aligned - A load/store instruction would have generated a memory
address that was not properly aligned according to the instruction, or a JMPL or RETT
instruction would have generated a non-word-aligned address.
• fp_exception - An FPU instruction generated an IEEE_754_exception and its corresponding
trap enable mask (TEM) bit was 1, or the FPU instruction was unimplemented, or the FPU
instruction did not complete, or there was a sequence or hardware error in the FPU. The
type of floating-point exception is encoded in the FSRJFTT.
• data_access_exception - A blocking error exception occurred on a load/store data access.
EDAC uncorrectable error.
• tag_overflow - A tagged arithmetic instruction was executed, and either arithmetic overflow
occurred or at least one of the tag bits of the operands was non zero.
• trap_division_by_zero - An integer divide instruction attempted to divide by zero.
• trap_instruction - A software instruction (Ticc) was executed and the trap condition
evaluated to true.
When multiple synchronous traps occur at the same cycle (i.e hardware errors), the highest pri-
ority trap is taken, and lower priority traps are ignored.
22 _{AT697F ADVANCE INFORMATION}
7703C–AERO–6/09