AT697F Datasheet, PDF (65/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697F ADVANCE INFORMATION
DSU
Communication
Link
DSU communication link consists of a UART connected to the internal bus as a master.
Figure 39. DSU Communication Link Block Diagram
Baud-rate
generator
8*bitclk
Serial port
Controller
AMBA APB
DSURX
Receiver shift register
Transmitter shift register
DSUTX
Data Frame
AHB master interface
AHB data/response
AMBA AHB
A simple communication protocol is supported to transmit access parameters and data. A link
command consist of a control byte, followed by a 32-bit address, followed by optional write data.
If the TBCJLR is set, a response byte will be sent after each AHB transfer. If the TBCJLR is not
set, a write access does not return any response, while a read access only returns the read
data.
Data is sent on 8-bit basis.
Figure 40. DSU UART Data Frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
Commands
Through the communication link, a read or write transfer can be generated to any address on the
internal bus. A response byte is can optionally be sent when the processor goes from execution
mode to debug mode. Block transfers can be performed be setting the length field to n-1, where
n denotes the number of transferred words. For write accesses, the control byte and address is
sent once, followed by the number of data words to be written. The address is automatically
incremented after each data word. For read accesses, the control byte and address is sent once
and the corresponding number of data words is returned.
Figure 41. DSU Commands
DSU Write Command
Send 11 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Addr[7:0] Data[31:24] Data[23:16] Data[15:8] Data[7:0]
Receive
Resp. byte (optional)
DSU Read command
Send 10 Length -1 Addr[31:24] Addr[23:16] Addr[15:8]
Addr[7:0]
Response byte encoding
bit 7:3 = 000000
bit 2 = DMODE
bit 1:0 = HRESP
Receive _{Data[31:24] Data[23:16] Data[15:8] Data[7:0]}
Resp. byte (optional)
Clock Generation
The UART contains a 14-bit down-counting scaler to generate the desired baud-rate. The scaler
is clocked by the system clock and generates a UART tick each time it underflows. The scaler is
reloaded with the value of the UART scaler reload register after each underflow. The resulting
UART tick frequency should be 8 times the desired baud-rate.
65
7703C–AERO–6/09