AT697F Datasheet, PDF (130/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AC Characteristics The AT697 processor implements a single event transient protection mechanism. The influence
of this protection is reflected by the timing figures presented in the following tables.
The following tables show the timing figures for the skew condition natural and maximum.
Natural Skew
Test Conditions
Parameter
t1
t1_p
t2
t2_p
t3
t4
t5
t6
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
• Natural Skew
• Temperature range : -55°C to 125°C
• Voltage range :
– I/O: 3.3V +/- 0.30V
– Core: 1.8V +/- 0.15V
• Output load : 30pF
Table 126. AC Characteristics - Natural Skew
Min Max
(ns) (ns)
Comment
10
CLK Period with PLL disable
40
57
CLK Period with PLL enable
4.5
CLK Low and High pulse width - PLL disabled
18
CLK Low and High pulse width - PLL enabled
10
SDCLK Period
3.5
7
1.10⁷
SDCLK output delay - PLL disabled
PLL setup time
1*t3
Reset Pulse Width
1.5
7
A[27:0] output delay
1.5
8
D[31:0] and CB[7:0] output delay
2
4
D[31:0] and CB[7:0] setup time
0
D[31:0] and CB[7:0] hold time during load/fetch
D[31:0] and CB[7:0] hold time during write
1.5
8
OE*, READ and WRITE* output delay
1
5
ROMS*[1:0] output delay
1.5
6
RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay
1.5
6
IOS* output delay
5
BRDY* setup time
0
BRDY* hold time
2.5
8.5
SDCAS* output delay
2.5
8.5
SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay
6
BEXC* setup time
0
BEXC* hold time
2.5
9
PIO[15:0] output delay
6
PIO[15:0] setup time
130 _{AT697F ADVANCE INFORMATION}
Reference edge
(‘+’ for rising edge)
CLK
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
7703C–AERO–6/09