AT697F Datasheet, PDF (61/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

DSU Breakpoint
Time Tag
Trace Buffer
Instruction trace
AT697F ADVANCE INFORMATION
• the timer unit is (optionally) stopped to freeze the AT697 timers and watchdog
The instruction that caused the processor to enter debug mode is not executed, and the proces-
sor state is kept unmodified. Execution is resumed by clearing the DSUCJBN or by de-
asserting DSUEN. The timer unit will be re-enabled and execution will continue from the saved
PC and nPC. Debug mode can also be entered after the processor has entered error mode, for
instance when an application has terminated and halted the processor. The error mode can be
reset and the processor restarted at any address.
The DSU contains two breakpoint registers for matching either internal bus addresses or exe-
cuted processor instructions. A breakpoint hit is typically used to freeze the trace buffer, but can
also put the processor in debug mode.
Freeze operation can be delayed by programming the DSUCJDCNT to a non-zero value. In this
case, the DSUCJDCNT value will be decremented for each additional trace until it reaches
zero, after which the trace buffer is frozen. If the brake on trace freeze bit DSUCJBT is set logi-
cal one, the DSU forces the processor into debug mode when the trace buffer is frozen.
Note: Due to pipeline delays, up to 4 additional instruction can be executed before the processor is
placed in debug mode.
A mask register is associated with each breakpoint, allowing breaking on a block of addresses.
Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint
detection.
The DSU implements a time tag counter. This counter is decremented each clock as long as the
processor is running. The counter is stopped when the processor enters debug mode. It is
restarted when execution is resumed.
This time tag counter is stored in the trace as an execution time reference.
The trace buffer consists of a circular buffer that stores the executed instructions or the internal
bus data transfers. The size of the trace buffer is 512 lines of 16 bytes. The trace buffer opera-
tion is controlled through the DSU control register (DSUC) and the trace buffer control register
(TBC). When the processor enters debug mode, tracing is suspended.
The trace buffer can contain the executed instructions, the transfers on the internal bus or both
(mixed-mode). The trace buffer control register (TBC) contains two counters TBCJBCNT and
TBCJICNT that store the address of the trace buffer location that will be written on next trace.
Since the buffer is circular, it actually points to the oldest entry in the buffer. The indexes are
automatically incremented after each stored trace entry.
The instruction trace mode is enabled setting logical one the trace instruction enable bit
TBCJTI.
During instruction tracing, one instruction is stored per line in the trace buffer with the exception
of multi-cycle instructions. Multi-cycle instructions can be entered two or three times in the trace
buffer :
• For store instructions, bits [63:32] correspond to the store address on the first entry and to
the stored data on the second entry (and third in case of STD). Bit 126 is set logical one on
the second and third entry to indicate this.
• A double load (LDD) is entered twice in the trace buffer, with bits [63:32] containing the
loaded data.
• Multiply and divide instructions are entered twice, but only the last entry contains the result.
Bit 126 is set for the second entry.
• For FPU operation producing a double-precision result, the first entry puts the MSB 32 bits
of the results in bit [63:32] while the second entry puts the LSB 32 bits in this field.
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