AT697F Datasheet, PDF (63/155 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697F ADVANCE INFORMATION
DSU Memory Map
Table 23. DSU Map
Address
0x800000c4
0x800000c8
0x800000cc
0x90000000
0x90000004
0x90000008
0x90000010
0x90000014
0x90000018
0x9000001C
0x90010000 - 0x90020000
..0
...4
...8
...C
0x90020000 - 0x90040000
0x90080000 - 0x90100000
0x90080000
0x90080004
0x90080008
0x9008000C
0x90080010
0x90080014
0x90080018
0x9008001C
0x90080040 - 0x9008007C
0x90100000 - 0x90140000
0x90140000 - 0x90180000
0x90180000 - 0x901C0000
0x901C0000 - 0x90200000
Register
DSU UART status register
DSU UART control register
DSU UART scaler register
DSU control register
Trace buffer control register
Time tag counter
AHB break address 1
AHB mask 1
AHB break address 2
AHB mask 2
Trace buffer
Trace bits 127 - 96
Trace bits 95 - 64
Trace bits 63 - 32
Trace bits 31 - 0
IU/FPU register file
IU special purpose registers
Y register
PSR register
WIM register
TBR register
PC register
NPC register
FSR register
DSU trap register
ASR16 - ASR31 (when implemented)
Instruction cache tags
Instruction cache data
Data cache tags
Data cache data
7703C–AERO–6/09
The addresses of the IU/FPU registersis defined according to how many register windows has
been implemented. The registers can be accessed at the following addresses (NWINDOWS =
number of SPARC register windows = 8):
• %on: 0x90020000 + (((psr.cwp * 64) + 32 + n) mod (NWINDOWS*64))
• %ln: 0x90020000 + (((psr.cwp * 64) + 64 + n) mod (NWINDOWS*64))
• %in: 0x90020000 + (((psr.cwp * 64) + 96 + n) mod (NWINDOWS*64))
• %gn: 0x90020000 + (NWINDOWS*64) + 128
• %fn: 0x90020000 + (NWINDOWS*64)
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