C511_1 Datasheet, PDF (84/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Units
6.4.8.2 SSC Interrupt Enable Register SCIEN
This byte addressable register enables or diasables interrupt request for the status bits.
This register must only be written when the SSC interrupts are disabled in the general interrupt
enable register IE (A8H), otherwise unexpected interrupt requests may occur.
Special Function Registers SCIEN (Address F9H)
MSB
Bit No. 7
6
5
4
3
F9H
–
–
–
–
–
Reset Value : XXXXXX00B
LSB
2
1
0
– WCEN TCEN SCIEN
Bit
–
WCEN
TCEN
Function
Not implemented. Reserved for future use. During reads these bits will be
undefined.
Write Collision Interrupt Enable
WCEN =0 : No interrupt request will be generated if the WCOL bit in the status
register SCF is set.
WCEN=1 : An interrupt is generated if the WCOL bit in the status register SCF is
set.
Transfer Completed Interrupt Enable
TCEN =0 : No interrupt request will be generated if the TC bit in the status
register SCF is set.
TCEN=1 : An interrupt is generated if the TC bit in the status register SCF is set.
Note: The SSC interupt behaviour is in addition affected by bit ESSC in the interrupt enable register
IE and by bit PSSC of the interrupt priority register IP.
Semiconductor Group
6-51