C511_1 Datasheet, PDF (80/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Units
6.4.7 Data/Clock Timing Relationships
The SSC provides four different clocking schemes for clocking the data in and out of the shift
register. Controlled by two bits in SSCCON, the clock polarity (idle state of the clock, control register
bit CPOL) and the clock/data relationship (phase control, control register bit CPHA), i.e. which clock
edges will be used for sample and shift. The following figures show the various possibilities.
6.4.7.1 Master Mode Operation
Figure 6-6-32 shows the clock/data/control relationship of the SSC in master mode. When CPHA
is set to 1, the MSB of the data that was written into the shift register will be provided on the
transmitter output after the first clock edge, the receiver input will sample with the next clock edge.
The direction (rising or falling) of the respective clock edge is depending on the clock polarity
selected. After the last bit has been shifted out, the data output STO will go to the high output level
(logic 1) and remain there until the next transmission is started. However, when enabling the SSC
after reset, the logic level of STO will be undefined, until the first transmission starts.
When CPHA is 0, the MSB will output immediately after the data was written into the shift register.
The first clock edge of SCLK will be used for sampling the input data, the next to shift out the next
bit. Between transmissons the data output STO will be "1".
Figure 6-32
Master Mode Operation of SSC
Semiconductor Group
6-47