C511_1 Datasheet, PDF (23/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
3.3 XRAM Operation (C513A/A-H only)
The XRAM is a memory area that is logically located in the external memory space, but is integrated
on the chip. Because the XRAM is used in the same way as external data memory the same
instruction types must be used for accessing the XRAM. The XRAM can be enabled and disabled
by the XMAP bit in the SYSCON register (see chapter 4.4).
3.3.1 Reset Operation of the XRAM
The content of the XRAM is not affected by a reset. After power-up the content is undefined, while
it remains unchanged during and after a reset as long as the power supply is not turned off.
If a reset occurs during a write operation to XRAM, the content of a XRAM memory location
depends on the cycle which the reset is detected at (MOVX is a 2-cycle instruction):
Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected.
Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.
After reset the XRAM is disabled.
3.3.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
There are a read and a write instruction to access the XRAM which use the 16-bit DPTR for indirect
addressing. The instructions are :
– MOVX A, @DPTR (Read)
– MOVX @DPTR, A (Write)
Use of these instructions normally implies, that port 0 is used as address low/data bus, port 2 for
high address output and parts of port 3 for control to access upto 64 KB of external memory. If the
XRAM is disabled, this will happen as with the other members of the C511/513 family. If it is enabled
and if the effective address is in the range of 0000H to FEFFH, these instruction also will access
external memory.
If XRAM is enabled and if the address is within FF00H to FFFFH, the physically internal XRAM of
the C513A/A-H will be accessed. Physically external memory in this address range cannot be
accessed in this case, because no external bus cycles will generated. Therefore port 0, 2 and 3 can
be used as general purpose I/O if only the XRAM memory space is addressed by the user program.
3.3.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)
The C511/513 architecture provides also instructions for accesses to external data memory which
use only an 8-bit address (indirect addressing with registers R0 or R1). These instructions are :
– MOVX A, @Ri
– MOVX @Ri, A
(Read)
(Write)
Use of these instructions implies, that port 0 is used as address/data bus, port 2 for high address
output and parts of port 3 for control. Normally these instructions are used to access up to 256 byte
of external memory.
If the XRAM is disabled, this will happen as with the other members of the C511/513 components
and the external memory is accessed.
Semiconductor Group
3-3