C511_1 Datasheet, PDF (77/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Units
As the SSC is a synchronous serial interface, for each transfer a dedicated clock signal sequence
must be provided. The SSC has implemented a clock control circuit, which can generate the clock
via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The
clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is
P1.2 / SCLK.
When operating in slave mode, a slave select input SLS is provided which enables the SSC
interface and also will control the transmitter output. The pin used for this is P1.5 / SLS. In addition
to this there is an additional option for controlling the transmitter output by software.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
6.4.2 General Operation of the SSC
After initialization of the SSC, the data to be transmitted has to be written into the shift register
STB.
In master mode this will initiate the transfer by resetting the baudrate generator and starting the
clock generation. The control bits CPOL and CPHA in the SSCCON register determine the idle
polarity of the clock (polarity between transfers) and which clock edges are used for shifting and
sampling data (see figure 6-6-32).
While the transmit data in the shift register is shifted out bit per bit starting with the MSB, the
incoming receive data are shifted in, synchronized with the clock signal at pin SCLK. When the eight
bits are shifted out (and the same number is of course shifted in), the contents of the shift register
is transferred to the receive buffer register SRB, and the transmission complete flag TC is set. If
enabled an interrupt request will be generated.
After the last bit has been shifted out and was stable for one bit time, the STO output will be switched
to "1" (forced "1"), the idle state of STO. This allows connection of standard asynchronous receivers
to the SSC in master mode.
In slave mode the device will wait for the slave select input SLS to be activated (=low) and then will
shift in the data provided on the receive input according to the clock provided at the SCLK input and
the setting of the CPOL ad CPHA bits. After eight bits have been shifted in, the content of the shift
register is transferred to the receive buffer register and the transmission complete flag TC is set. If
the transmitter is enabled in slave mode (TEN bit set to 1), the SSC will shift out at STO at the same
time the data currently contained in the shift register. If the transmitter is disabled, the STO output
will remain in the tristate state. This allows more than one slave to share a common select line.
If SLS is inactive the SSC will be inactive and the content of the shift register will not be modified.
6.4.3 Enable/Disable Control
Bit SSCEN of the SSCCON register globally enables or disables the synchronous serial interface.
Setting SSCEN to “0” stops the baud rate generator and all internal activities of the SSC. Current
transfers are aborted. The alternate output functions at pins P1.3/SRI, P1.4/STO, P1.5/SLS, and
P1.2/SCLK return to their primary I/O port function. These pins can now be used for general
purpose I/O.
Semiconductor Group
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