C511_1 Datasheet, PDF (81/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Units
6.4.7.2 Slave Mode Operation
Figure 6-6-33 shows the clock/data/control relationship of the SSC in slave mode. When SLS is
active (low) and CPHA is 1, the MSB of the data that was written into the shift register will be
provided on the transmitter output after the first clock edge (if the transmitter was enabled by setting
the TEN bit to 1), the receiver input will sample the input data with the next clock edge. The direction
(rising or falling) of the respective clock edge is depending on the clock polarity selected. In this
case (CPHA = 1) the SLS input may stay active during the transmission of consecutive bytes.
When CPHA = 0 and the transmitter is enabled, the MSB of the shift register is provided
immediately after the SLS input is pulled to active state (low). The receiver will sample the input with
the first clock edge, and the transmitter will shift out the next bit with the following clock edge. If the
transmitter is disabled the output will remain in the high impedancec state. In this case (CPHA=0),
correct operation requires that the SLS input to go inactive between consecutive bytes.
When SLS is inactive the internal shift clock is disabled and the content of the shift register will not
be modified. This also means that SLS must stay active until the transmission is completed.
If during a transmission SLS goes inactive before all eight bits are received, the reception process
will be aborted and the internal frame counter will be reset. TC will not be set in this case. With the
next activation of SLS a new reception process will be started.
Figure 6-33
Slave Mode Operation of SSC
Semiconductor Group
6-48