C511_1 Datasheet, PDF (83/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Units
Bit
Function
CPHA
Clock Phase
This bit controls in conjunction with the CPOL bit controls which clock edges are
used for sample and shift
CPHA=0 : The first clock edge of SCLK is used to sample the data, the second
to shift the next bit out at STO.
In master mode the transmitter will provide the first data bit on STO
immediately after the data was written into the STB register.
In slave mode the transmitter (if enabled via TEN) will shift out the
first data bit with the falling edge of SLS .
CPHA=1 : The first data bit is shifted out with the first clock edge of SCLK and
sampled with the second clock edge
BRS2,
Baudrate Selection Bits
BRS1, BRS0 These bits select one of the possible divide factors for generating the baudrate out
of the micrcontroller clock rate fosc . The baudrate is defined by .
Baudrate = -_D----_i-_v---_i--_df--^o-_e--^s-_f--^ca----_c---_t--_o---_r = -₄----_•----₂---_B-^f--^o-_R--^s--_S-^c--₍--₂----_–---₀---₎
for BRS (2-0) ≠ 0
BRS(2-0)
0
1
2
3
4
5
6
7
Divide
Factor
reserved
8
16
32
64
128
256
512
Example:
Baudrate for fosc
= 7.68 MHz
reserved
960 kBaud
480 kBaud
240 kBaud
120 kBaud
60 kBaud
30 kBaud
15 kBaud
Note: SSCCON must be programmed only when the SSC is idle. Modifying the contents of
SSCCON while a transmission is in progress will corrupt the current transfer and will lead to
unpredictable results.
Semiconductor Group
6-50