C511_1 Datasheet, PDF (121/128 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Device Specifications
Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA = 0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
Figure 10-4
SSC Timing
V_CC- 0.5V
0.45V
0.7 V_CC
0.2 V_CC- 0.1
Figure 10-5
External Clock Drive at XTAL1
t _CLCL
t _CHCL
t _CLCX
t _CLCH
t _CHCX
MCT00033
Semiconductor Group
10-9