AT17LV256 Datasheet, PDF (7/24 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

CE
GND
CEO
A2
READY
SER_EN
V_CC
AT17LV65/128/256/512/010/002/040
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between V_CC and GND is recommended.
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of
one device must be connected to the CE input of the next device in the chain. It will stay
Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin
is used.
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V_CC.
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
7
2321E–CNFG–06/03