AT17LV256 Datasheet, PDF (21/24 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

20S2 – SOIC
AT17LV65/128/256/512/010/002/040
C
1
EH
N
Top View
A1
End View
e
b
A
D
Side View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM
A
0.0926
A1
0.0040
b
0.0130
C
0.0091
D
0.4961
E
0.2914
H
0.3940
L
0.0160
e
0.050 BSC
MAX
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
0.4190
0.050
NOTE
4
1
2
3
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024") per side.
1/9/02
2325 Orchard Parkway
R San Jose, CA 95131
TITLE
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
DRAWING NO. REV.
20S2
A
21
2321E–CNFG–06/03