AT17LV256 Datasheet, PDF (5/24 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Block Diagram
SER_EN
WP1⁽²⁾
WP2⁽²⁾
AT17LV65/128/256/512/010/002/040
POWER ON
RESET
Device Description
2321E–CNFG–06/03
READY⁽²⁾
(1)
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
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