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AT17LV256 Datasheet, PDF (12/24 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory
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AC Characteristics
VCC = 3.3V ± 10%
AT17LV65/128/256
AT17LV512/010/002/040
Commercial
Industrial
Commercial
Industrial
Symbol Description
Min Max Min Max Min Max Min Max
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(to guarantee proper counting)
50
55
50
55
60
60
55
60
75
80
55
60
0
0
0
0
55
55
50
50
25
25
25
25
25
25
25
25
35
60
30
35
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
0
0
THOE
FMAX
Notes:
OE High Time (guarantees counter is reset)
25
25
25
25
Maximum Clock Frequency
10
10
15
10
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
AC Characteristics when Cascading
VCC = 3.3V ± 10%
AT17LV65/128/256
AT17LV512/010/002/040
Commercial
Industrial
Commercial
Industrial
Symbol
TCDF(2)
TOCK(1)
TOCE(1)
TOOE(1)
FMAX
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
Min Max Min Max Min Max Min Max
60
60
50
50
55
60
50
55
55
60
35
40
40
45
35
35
10
8
8
12.5
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
MHz
12 AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
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