AT17LV256 Datasheet, PDF (2/24 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Pin Configuration
8-lead LAP
DATA 1
CLK 2
(WP⁽¹⁾) RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
8-lead SOIC
DATA 1
8
CLK 2
7
(WP⁽¹⁾) RESET/OE 3
6
CE 4
5
VCC
SER_EN
CEO (A2)
GND
8-lead PDIP
DATA 1
CLK 2
(WP⁽¹⁾) RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
20-lead PLCC
CLK 4
(WP1⁽²⁾) NC 5
(WP⁽¹⁾) RESET/OE 6
(WP2⁽²⁾) NC 7
CE 8
18 NC
17 SER_EN
16 NC
15 NC (READY⁽²⁾)
14 CEO (A2)
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
2 AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03