AT17C002 Datasheet, PDF (7/19 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

AT17C/LV002
For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration
EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf.
Figure 3. In-System Programming of AT17 Series for PSLI Applications
V_CC V_CC
4.7 k9
4.7 k9
DATA 1
SCLK 3
5
7
9
2
4 ^VCC
6
8
10
GND
RESET
AT40K/AT40KAL/AT94K
RESET
M2
M1
M0
DATA0
CCLK
CON
INIT
AT17 Series Device
DATA
SER_EN
CLK
CE
RESET/OE⁽¹⁾ READY⁽²⁾
SER_EN
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications
V_CC V_CC
4.7 k9
4.7 k9
PROGRAM
V_CC
4.7 k9
XILINX FPGA
PROGRAM
M2
M1
M0
DIN
CCLK
DONE⁽³⁾
INIT
V_CC
4.7 k9
AT17 Series Device
DATA
SER_EN
CLK
CE
RESET/OE⁽¹⁾ READY⁽²⁾
DATA 1
SCLK 3
5
7
9
2
4 ^VCC
6
8
10
GND _{SER_EN}
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
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2281D–12/01