AT17C002 Datasheet, PDF (6/19 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
RESET
AT40K/AT40KAL/AT94K
RESET
M2
M1
M0
DATA0
CCLK
CON
INIT
AT17 Series Device
V_CC
DATA
SER_EN
CLK
CE
RESET/OE⁽¹⁾ READY⁽²⁾
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s inter-
nal address pointer so that the reconfiguration starts at the beginning.
Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
V_CC
PROGRAM
XILINX FPGA
PROGRAM
M2
M1
M0
DIN
CCLK
DONE⁽³⁾
INIT
4.7 k9
AT17 Series Device
V_CC
DATA
SER_EN
CLK
CE
RESET/OE⁽¹⁾ READY⁽²⁾
GND
Notes: 1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
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