AT17C002 Datasheet, PDF (4/19 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Pin Configurations
8
LAP
Pin
20
PLCC
Pin
44
TQFP
Pin
44
PLCC
Pin
Name
I/O Description
1
2
40
2
DATA
I/O Three-state DATA output for configuration. Open-collector bi-directional
pin for programming.
2
4
43
5
–
5
7
7
CLK
WP1⁽¹⁾
I Clock input. Used to increment the internal address and bit counter for
reading and programming.
I WRITE PROTECT (1). Used to protect portions of memory during
programming. Disabled by default due to internal pull-down resistor.
This input pin is not used during FPGA loading operations.
3
6
13
19
RESET/OE
I Output Enable (active High) and RESET (active Low) when SER_EN is
High. A Low level on RESET/OE resets both the address and bit
counters. A High level (with CE Low) enables the data output driver. The
logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
4
8
15
21
CE
I Chip Enable input (active Low). A Low level (with OE High) allows DCLK
to increment the address counter and enables the data output driver. A
High level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode
(SER_EN Low).
5
10
18
24
GND
Ground pin. A 0.2 µF decoupling capacitor between V_CC and GND is
recommended.
6
14
21
27
CEO
O Chip Enable Output (active Low). This output goes Low when the
address counter has reached its maximum value. In a daisy chain of
AT17 Series devices, the CEO pin of one device must be connected to
the CE input of the next device in the chain. It will stay Low as long as
CE is low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I Device selection input, A2. This is used to enable (or select) the device
during programming (i.e., when SER_EN is Low). A2 has an internal
pulldown resistor.
–
15
23
29
READY⁽¹⁾
O Open collector reset state indicator. Driven Low during power-up reset,
released when power-up is complete. (Recommend a 4.7 kΩ pull-up on
this pin if used).
7
8
Note:
17
35
41
SER_EN
I Serial enable must be held High during FPGA loading operations.
Bringing SER_EN Low enables the 2-wire Serial Programming Mode.
For non-ISP applications, SER_EN should be tied to V_CC.
20
38
44
V_CC
+3.3V/+5V power supply pin.
1. This pin is not available on the 8-lead packages.
4 AT17C/LV002
2281D–12/01