AT17C002 Datasheet, PDF (2/19 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Pin Configuration
8-lead LAP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
44-lead PLCC
20-lead PLCC
CLK 4
WP1 5
RESET/OE 6
NC 7
CE 8
18 NC
17 SER_EN
16 NC
15 READY
14 CEO(A2)
44-lead TQFP
WP1 7
NC 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
NC 15
NC 16
NC 17
39 NC
38 NC
37 NC
36 NC
35 NC
34 NC
33 NC
32 NC
31 NC
30 NC
29 READY
NC 1
NC 2
NC 3
NC 4
NC 5
NC 6
WP1 7
NC 8
NC 9
NC 10
NC 11
33 NC
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 NC
23 READY
2 AT17C/LV002
2281D–12/01