AT17C002 Datasheet, PDF (12/19 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

AC Characteristics for AT17LV002
V_CC = 3.3V ± 10%
Commercial
Industrial/Military⁽¹⁾
Symbol Description
Min
Max
Min
Max
Units
T_OE(2)
T_CE(2)
T_CAC(2)
OE to Data Delay
CE to Data Delay
CLK to Data Delay
50
55
ns
55
60
ns
55
60
ns
T_OH
T_DF(3)
Data Hold From CE, OE or CLK
CE or OE to Data Float Delay
0
0
ns
50
50
ns
T_LC
CLK Low Time
25
25
ns
T_HC
CLK High Time
25
25
ns
T_SCE
CE Setup Time to CLK (to guarantee proper counting)
30
35
ns
T_HCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
T_HOE
OE High Time (guarantees counter is reset)
25
25
ns
F_MAX
Notes:
Maximum Input Clock Frequency
15
10
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
MHz
AC Characteristics for AT17LV002 when Cascading
V_CC = 3.3V ± 10%
Commercial
Industrial/Military⁽¹⁾
Symbol Description
Min
Max
Min
Max
Units
T_CDF(3)
CLK to Data Float Delay
50
50
T_OCK(2)
T_OCE(2)
CLK to CEO Delay
CE to CEO Delay
50
55
35
40
T_OOE(2)
RESET/OE to CEO Delay
35
35
F_MAX
Notes:
Maximum Input Clock Frequency
12.5
10
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
ns
ns
ns
ns
MHz
12 AT17C/LV002
2281D–12/01